National Review
๋ณด์ ์ฑํฅ
IT/๊ธฐ์
โAI Obsessionโ Is a Big Nothing Burger
Before we know it, worries about AI-besotted partners are going to seem really dated.
๐บ๐ธ ๋ฏธ๊ตญ ยท IT/๊ธฐ์ ยท "RGER" ยท ์ด 25๊ฑด
ํํฐ ๋ณด๊ธฐํ์ฌ ์ง์
50.0
0 = ๋ถ์ ์ฐ์ธ
50 = ์ค๋ฆฝ
100 = ๊ธ์ ์ฐ์ธ
์ต๊ทผ 7์ผ ๊ธฐ์ค 10,703๊ฑด์ ๋ถ์ํ ๊ฒฐ๊ณผ, ๋ด์ค ์ฌ๋ฆฌ์ง์๋ 50.0(๊ท ํ)์ ๋๋ค. ๊ธ์ 1๊ฑด(0.0%)ยท์ค๋ฆฝ 10,701๊ฑด(100.0%)ยท๋ถ์ 1๊ฑด(0.0%)์ด๋ฉฐ, ์ค๋ฆฝ ๋น์ค์ด ๋๋ ทํ๊ฒ ๋์ต๋๋ค. ์ฑํฅ ์ง์๋ ์ข ํฉ 18.8(์ค๋ ๊ท ํ)์ ๋๋ค.
Before we know it, worries about AI-besotted partners are going to seem really dated.
People worry about the ways artificial intelligence will change jobs, education, creativity, and daily lives, according to polling. But they harbor skepticism about the ability of government to regulate it โ and rightfully so. Therefore, itโs particularly concerning when prominent thought leaders and lawmakers crusade for larger roles for the state in AI. For example, [โฆ]
SAG-AFTRA members have ratified a four-year contract with the major studios, which includes new provisions on synthetic actors and a merger of the unionโs two pension funds. Of those who cast ballots, 91.4% voted in favor of the contract and 8.6% were opposed. Turnout was 19.3% of eligible members. The contract allows producers to use [โฆ]
As AI systems grow larger, photonics is emerging as a faster, more efficient alternative to copper connections.
The ride-hailing company made an unreported follow-on investment in Nuro larger than its first, with remaining funds tied to driverless testing and passenger milestones
Keep your trio of Apple gadgets powered up wherever you go with these compact folding chargers.
AI firms heavily use news and other creative content to provide answers โ but New York Times Publisher A.G. Sulzberger says their resistance to pay for it amounts to a repackaging of โstolen goods.โ
Thermacell has launched Liv 2.0, the next generation of its Wi-Fi-connected smart mosquito protection system. It features new hardware and can cover a larger area, and Thermacell says its formula can now deter no-see-ums. But it's also more expensive and requires professional installation. Liv 2.0 uses the same setup as the original Liv - a [โฆ]
New York Times publisher A.G. Sulzberger warned that AI companies were making choices that could lead to โa great deal of unnecessary harmโ to the news business and the publicโs access to reliable sources, in a speech delivered during the World News Media Congress in France on Monday. Companies leading the development of generative-AI systems โ including [โฆ]
The AI-Driven Enterprise Institute released new research that breaks down how well S&P 500 companies are adopting AI compared to their peers.
Comments
As handheld consoles continue to grow and push the limits of what you can actually hold in your hands, the Arduboy FX-C comes in a refreshingly pocketable package. It manages to squeeze the best features of past models and some welcome upgrades into a handheld thatโs still no larger or thicker than a few credit [โฆ]
If youโre looking for a fast iPhone or AirPods charger thatโs easy to toss into your purse, backpack, or carry-on, Ankerโs Zolo Magnetic Wireless Charger is a smart pick. Itโs tiny and comes with a built-in USB-C cable, and you currently can buy two for $23.99 ($16 off) at Amazon and Anker (with code WS7DV2PK68EW), [โฆ]
Stop fumbling for cables in the dark. These WIRED-tested stands and pads will take the hassle out of refueling your phone, wireless earbuds, and watch.
Liz Centoni, Cisco's chief customer experience officer, is working to reinvent her 20,000-employee division for the AI era. "It's painful," she says.
New features coming to YouTube could make it better for listening to podcasts, rolling out to Premium subscribers starting today on Android and coming later to iOS. A new "on-the-go mode" shifts YouTube into an audio-first layout, with larger, simplified playback buttons, a still image in place of the video, and a timeline showing video [โฆ]
I have been an application-specific IC (ASIC) designer for almost three decades. Over that time, Iโve moved through the full academic trajectory, from graduate student to full professor; later, I transitioned to industry after an unsuccessful stint at entrepreneurship. When I made the switch to the private sector in 2019, I began focusing on a critically important aspect of the electronic industry: silicon intellectual property. As much as 80 percent of the physical area in todayโs most advanced chips is occupied by blocks that arenโt made for specific products or even designed by the consumer-facing companies that built them. Instead, chipmakers draw heavily on established silicon IP from companies like Arm, Cadence, Rambus, Synopsys, and the company I work for, Silicon Creations. Throughout my career, Iโve designed chips for very different purposes, including enabling the research program in my academic lab and expanding the IP portfolio of my company. When I joined Silicon Creations, I had no idea how differently the industry approaches IC design and encountered a steep learning curve. Initially, it seemed that much of my two decades of academic research and training did not directly translate to the role. I had to learn new skills and adopt a new mindset. Today, demand for ASICs is rapidly growing, driven by the need for specialized chips in the automotive sector, AI applications, and more. By one market estimate, the ASIC market is expected to grow from US $23.4 billion to $38.8 billion by 2033, and the semiconductor industry as a whole is projected to hit $1 trillion by 2030. The industry needs more chip designersโbut if youโre coming from an academic background as I did, there are a few things youโll need to know. Different goals lead to different strategies The differences between industry and academe begin with a divergence in purpose. In academia, my primary objective was to generate new knowledge: to propose a novel circuit technique, validate an unconventional architecture, or explore the limits of performance in a given domain. A successful chip is one that demonstrates a concept. In industry, it is not nearly enough to prove that something can work. The goal is to ensure that it works reliably, repeatedly, and at scale. Success is measured not by novelty but by whether the silicon meets specifications, yields as expected in production, and supports a competitive product delivered on schedule. This leads to a stark contrast in risk tolerance. Academic designs often deliberately push into unproven territory, where even partial success can yield valuable insight. In industry, however, we systematically minimize risk. The cost of failure makes first-time silicon success a central requirementโespecially at advanced technology nodes, where the lithography masks used to transfer circuit designs onto silicon wafers alone can cost tens of millions of dollars. As a result, industry design flows are built around eliminating uncertainty through conservative margins, extensive validation, and careful reuse of proven solutions. โAcademia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale.โ This paradigm has existed since the 1970s, when application-specific chip design was established. However, the gulf between academia and industry has expanded since the mid-2010s, when FinFET technology, a 3D architecture using vertical โfinsโ of silicon, was widely adopted in industry. System designs are also becoming increasingly modular with the advent of chiplets. This fundamentally altered the economics and complexity of ASIC development, with design costs rising by almost an order of magnitude. Initiatives like Taiwan Semiconductor Manufacturing Co.โs University FinFET Program and new government-funded chip-design hubs now let some well-resourced universities design for more advanced architectures, but the technology is still out of reach for many academics. What the industry-academia split means in practice Consider a startup developing an ASIC. Its engineering team may have deep expertise in a particular algorithm, sensor interface, or system architecture, the features that define its competitive advantage. But it is unlikely to possess world-class expertise in every supporting function. Developing each of these blocks internally would require significant time, capital, and specialized talent. Doing so could delay market entry beyond the startupโs viability. Even large semiconductor companies face similar constraints. Advanced-node development demands intense focus. Allocating a team to redesign a standard interface block that has already been implemented elsewhere may be difficult to justify when differentiation lies at the system level, such as an inference chipโs ability to speed up neural network computations. The time it takes to move a new chip from conception to market and risk mitigation, not self-sufficiency, govern most decisions about in-house development versus outsourcing. The economics of advanced IC manufacturing reinforce this reality. When the development cost of a leading-edge chip reaches hundreds of millions of dollars, minimizing risk becomes a central design imperative. In this context, silicon IP emerged as a practical solution. Similar to how software developers rely on preexisting libraries rather than writing every function from scratch, ASIC designers license predesigned, preverified silicon blocksโsuch as processor cores, memory interfaces, and security enginesโfrom highly specialized IP vendors. These blocks can then be integrated into larger, increasingly complex systems. Design scope, verification, and time horizons With the use of silicon IP, industry is able to widen the scope of its designs. Academic efforts tend to focus on block-level innovation: a new analog-to-digital converter architecture or an ultralow-noise amplifier, for instance. These designs typically abstract away many of the complexities of bringing a chip to market, such as packaging constraints, long-term reliability, and manufacturing yield. In industry, the focus shifts to system-level integration. Modern systems on chips, or SoCs, incorporate dozens or even hundreds of functional blocks. Managing signal integrity, timing, firmware interaction, and system-level validation becomes as critical as the design of any individual block. Verification philosophy also diverges sharply. In academia, the goal of verification is to demonstrate that the concept works under nominal conditions, which may not always reflect how it would perform in real applications. Even if only a fraction of fabricated chips from a multiproject wafer operates correctly, the design may still be considered a success if it validates the underlying idea. At my academic lab for instance, we used to receive 40 chips from a TSMC prototyping service and started testing them in batches of five. If the first five or 10 chips proved functional, we had already collected more than enough data for a publication. If some of them failed, we werenโt required to mention this when publishing the results. In industry, verification is exhaustive, critical, and often dominates the development schedule. Failures are measured in parts per million, and even rare anomalies are carefully analyzed and documented to identify root causes and prevent recurrence. When I started at Silicon Creations, I was surprised by the level of detail and scrutiny designs face. Differences in time horizons and economic constraints reinforce each of these contrasts. Academic projects operate on flexible timelines aligned with research and funding cycles. If I missed a deadline, I just had to wait for the next cycle. Industry projects are driven by fixed product schedules and market windows, frequently targeting costly leading-edge nodes to achieve competitive performance, power, and area efficiency. Missing a deadline can negate the value of an entire design and may have major financial consequences along the entire supply chain. In essence, academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale. Both are indispensable, but they operate under fundamentally different definitions of success. As ASIC complexity continues to grow, understanding both perspectives will be essential for the next generation of engineers navigating the evolving semiconductor landscape. This article appears in the June 2026 print issue.
Massive OLED TVs and Sonos speakers might be stealing the Memorial Day spotlight, but there are also plenty of great deals that won't set you back nearly as much. In fact, some of the best discounts we're seeing are on gadgets that retail for $50 or less, from portable chargers and 4K streaming devices to [โฆ]
Keep the charging puckโs exposed pins far away from anything metal.
Discover how the ZEISS Crossbeam 750 FIBSEM sets a new benchmark for precise TEM lamella prep, tomography, and advanced nanofabrication. This delivers better resolution, better SNR, larger usable FOV, and shorter acquisition times. Learn how uninterrupted FIB milling will reduce damage and rework, accelerate time to TEM, and increase first pass successโso your FA, yield, and materials teams make faster, confident data driven decisions. Join us to discover how the new ZEISS Crossbeam 750 with its see while you mill capability delivers precision and clarityโevery timeโfor demanding FIB-SEM workflows. Designed for extremely challenging TEM lamella preparation, tomography, advanced nanofabrication, and APTโready liftโout, Crossbeam 750 combines a new Gemini 4 SEM objective lens, a double deflector, and a nextโgeneration scan generator to elevate both image quality and process confidence. Youโll learn how better resolution and better SNR translate into more image detail and shorter acquisition times, while the lowโkV FIB performance enables more precise lamella prep. Weโll demonstrate High Dynamic Range (HDR) Mill + SEMโan interwoven SEM/FIB scanning mode that suppresses FIBโgenerated background. This enables immediate, clean visual feedback, even during nudging the FIB pattern live while milling . The result: confident endpointing with uninterrupted FIB milling and pristine, metrologyโgrade surfaces with the lowest possible sample damage. This session is ideal for semiconductor failure analysists, yield teams and materials scientists seeking faster timeโtoโTEM, higher firstโpass success, and consistent outcomes at low kV. See how Crossbeam 750 empowers you to make earlier stopโmilling decisions, cut rework, and reliably plan turnaround timeโso you can move from sample to insight with confidence. Register now for this free webinar!