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CRDTs merge concurrent edits. Why not concurrent creation?
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๐บ๐ธ ๋ฏธ๊ตญ ยท IT/๊ธฐ์ ยท "CREATION" ยท ์ด 13๊ฑด
ํํฐ ๋ณด๊ธฐํ์ฌ ์ง์
49.7
0 = ๋ถ์ ์ฐ์ธ
50 = ์ค๋ฆฝ
100 = ๊ธ์ ์ฐ์ธ
์ต๊ทผ 7์ผ ๊ธฐ์ค 1,441๊ฑด์ ๋ถ์ํ ๊ฒฐ๊ณผ, ๋ด์ค ์ฌ๋ฆฌ์ง์๋ 49.7(๊ท ํ)์ ๋๋ค. ๊ธ์ 87๊ฑด(6.0%)ยท์ค๋ฆฝ 1,227๊ฑด(85.1%)ยท๋ถ์ 127๊ฑด(8.8%)์ด๋ฉฐ, ์ค๋ฆฝ ๋น์ค์ด ๋๋ ทํ๊ฒ ๋์ต๋๋ค. ์ฑํฅ ์ง์๋ ์ข ํฉ -5.8(์ค๋ ๊ท ํ)์ ๋๋ค.
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AI as we know it has been used for everything from making full-length feature films to solving nearly impossible math problems. But today AI is also, relatively speaking, just a child. That said, AI is a child that has learned languages, how to play games, how to blackmail people, how to power robots and, in [โฆ]
Chase McGill and Matt Dragstrem, two hit Nashville writers, defend their flesh-and-blood creation "Fish Hunt Golf Drink": "Itโs not rocket science, but itโs true to who Luke is"
Depending on who you talk to, AI is either the future, a cheap parlor trick or the death of creativity as we know it. But at this weekโs โAI on the Lotโ conference, up and coming filmmakers, developers and wanna-be showbiz entrepreneurs were all banking that AI will be their on-ramp into an insular business....
The โAmerican Gigoloโ and โFirst Reformedโ director believes โus carbon-based foolsโ will โspend our money empathizing and caring about silicon-based creations.โ
'Whispers,' the latest tech-fueled creation from Emmy winner Bernie Su, synthesizes AI prompts from its audience to generate a unique experience.
An AI company announced this week that it is digitally resurrecting famed Marvel creator Stan Lee and charging users for access to his recreated voice and likeness. ElevenLabs revealed Wednesday that the late comic book writerโs AI-generated voice and image will be added to its growing collection of celebrity recreations that can be licensed for ...
I have been an application-specific IC (ASIC) designer for almost three decades. Over that time, Iโve moved through the full academic trajectory, from graduate student to full professor; later, I transitioned to industry after an unsuccessful stint at entrepreneurship. When I made the switch to the private sector in 2019, I began focusing on a critically important aspect of the electronic industry: silicon intellectual property. As much as 80 percent of the physical area in todayโs most advanced chips is occupied by blocks that arenโt made for specific products or even designed by the consumer-facing companies that built them. Instead, chipmakers draw heavily on established silicon IP from companies like Arm, Cadence, Rambus, Synopsys, and the company I work for, Silicon Creations. Throughout my career, Iโve designed chips for very different purposes, including enabling the research program in my academic lab and expanding the IP portfolio of my company. When I joined Silicon Creations, I had no idea how differently the industry approaches IC design and encountered a steep learning curve. Initially, it seemed that much of my two decades of academic research and training did not directly translate to the role. I had to learn new skills and adopt a new mindset. Today, demand for ASICs is rapidly growing, driven by the need for specialized chips in the automotive sector, AI applications, and more. By one market estimate, the ASIC market is expected to grow from US $23.4 billion to $38.8 billion by 2033, and the semiconductor industry as a whole is projected to hit $1 trillion by 2030. The industry needs more chip designersโbut if youโre coming from an academic background as I did, there are a few things youโll need to know. Different goals lead to different strategies The differences between industry and academe begin with a divergence in purpose. In academia, my primary objective was to generate new knowledge: to propose a novel circuit technique, validate an unconventional architecture, or explore the limits of performance in a given domain. A successful chip is one that demonstrates a concept. In industry, it is not nearly enough to prove that something can work. The goal is to ensure that it works reliably, repeatedly, and at scale. Success is measured not by novelty but by whether the silicon meets specifications, yields as expected in production, and supports a competitive product delivered on schedule. This leads to a stark contrast in risk tolerance. Academic designs often deliberately push into unproven territory, where even partial success can yield valuable insight. In industry, however, we systematically minimize risk. The cost of failure makes first-time silicon success a central requirementโespecially at advanced technology nodes, where the lithography masks used to transfer circuit designs onto silicon wafers alone can cost tens of millions of dollars. As a result, industry design flows are built around eliminating uncertainty through conservative margins, extensive validation, and careful reuse of proven solutions. โAcademia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale.โ This paradigm has existed since the 1970s, when application-specific chip design was established. However, the gulf between academia and industry has expanded since the mid-2010s, when FinFET technology, a 3D architecture using vertical โfinsโ of silicon, was widely adopted in industry. System designs are also becoming increasingly modular with the advent of chiplets. This fundamentally altered the economics and complexity of ASIC development, with design costs rising by almost an order of magnitude. Initiatives like Taiwan Semiconductor Manufacturing Co.โs University FinFET Program and new government-funded chip-design hubs now let some well-resourced universities design for more advanced architectures, but the technology is still out of reach for many academics. What the industry-academia split means in practice Consider a startup developing an ASIC. Its engineering team may have deep expertise in a particular algorithm, sensor interface, or system architecture, the features that define its competitive advantage. But it is unlikely to possess world-class expertise in every supporting function. Developing each of these blocks internally would require significant time, capital, and specialized talent. Doing so could delay market entry beyond the startupโs viability. Even large semiconductor companies face similar constraints. Advanced-node development demands intense focus. Allocating a team to redesign a standard interface block that has already been implemented elsewhere may be difficult to justify when differentiation lies at the system level, such as an inference chipโs ability to speed up neural network computations. The time it takes to move a new chip from conception to market and risk mitigation, not self-sufficiency, govern most decisions about in-house development versus outsourcing. The economics of advanced IC manufacturing reinforce this reality. When the development cost of a leading-edge chip reaches hundreds of millions of dollars, minimizing risk becomes a central design imperative. In this context, silicon IP emerged as a practical solution. Similar to how software developers rely on preexisting libraries rather than writing every function from scratch, ASIC designers license predesigned, preverified silicon blocksโsuch as processor cores, memory interfaces, and security enginesโfrom highly specialized IP vendors. These blocks can then be integrated into larger, increasingly complex systems. Design scope, verification, and time horizons With the use of silicon IP, industry is able to widen the scope of its designs. Academic efforts tend to focus on block-level innovation: a new analog-to-digital converter architecture or an ultralow-noise amplifier, for instance. These designs typically abstract away many of the complexities of bringing a chip to market, such as packaging constraints, long-term reliability, and manufacturing yield. In industry, the focus shifts to system-level integration. Modern systems on chips, or SoCs, incorporate dozens or even hundreds of functional blocks. Managing signal integrity, timing, firmware interaction, and system-level validation becomes as critical as the design of any individual block. Verification philosophy also diverges sharply. In academia, the goal of verification is to demonstrate that the concept works under nominal conditions, which may not always reflect how it would perform in real applications. Even if only a fraction of fabricated chips from a multiproject wafer operates correctly, the design may still be considered a success if it validates the underlying idea. At my academic lab for instance, we used to receive 40 chips from a TSMC prototyping service and started testing them in batches of five. If the first five or 10 chips proved functional, we had already collected more than enough data for a publication. If some of them failed, we werenโt required to mention this when publishing the results. In industry, verification is exhaustive, critical, and often dominates the development schedule. Failures are measured in parts per million, and even rare anomalies are carefully analyzed and documented to identify root causes and prevent recurrence. When I started at Silicon Creations, I was surprised by the level of detail and scrutiny designs face. Differences in time horizons and economic constraints reinforce each of these contrasts. Academic projects operate on flexible timelines aligned with research and funding cycles. If I missed a deadline, I just had to wait for the next cycle. Industry projects are driven by fixed product schedules and market windows, frequently targeting costly leading-edge nodes to achieve competitive performance, power, and area efficiency. Missing a deadline can negate the value of an entire design and may have major financial consequences along the entire supply chain. In essence, academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale. Both are indispensable, but they operate under fundamentally different definitions of success. As ASIC complexity continues to grow, understanding both perspectives will be essential for the next generation of engineers navigating the evolving semiconductor landscape. This article appears in the June 2026 print issue.
But there are some real-world constraints that virtual pinball could easily ignore.
The OnCampus program, administered by IEEE Educational Activities, last year expanded its engineering experiences from two to seven universities. Part of TryEngineering, the program is held at universities around the world, offering preuniversity students hands-on opportunities to solve engineering problems. The IEEE Innovation Committee provided funding for the additional locations. New participating institutions The electrical engineering and computing faculty at the University of Zagreb, in Croatia, hosted a two-day program in June. Twenty-five children ages 10 to 14 participated in lectures and workshops on artificial intelligence, computer science, robotics, and astronomy. Tomislav Jaguลกt, an IEEE senior member and the chair of the IEEE preuniversity coordinating committee, led the program. In September the Arab Academy for Science, Technology, and Maritime Transportโs engineering college held a two-day session at its Abu Kir, Egypt, campus. Fifty students participated in hands-on activities on Ohmโs law, radio communications, and circuit building. They also learned from professors about engineering careers and job opportunities. Also in September, the Majan University College, in Muscat, Oman, hosted 40 high school students who competed in six challenges to design and build circuits. These include an IoT design and an LED brightness control using a potentiometer, a three-terminal, manually adjustable resistor that functions as a variable voltage divider. The program also highlighted AI and quantum computing technologies and introduced students to job opportunities in the fields. The workshop transformed curiosity into creation, empowering students with technical skills and confidence in emerging technologies. In November at the Universiti Malaysia Perlis, in Arau, 50 students explored the fundamentals of quantum computational intelligence and AI through hands-on activities and interactive simulations. IEEE Senior Member Mohd Hafiz Ismail, a professor of electronic engineering and technology, gave an introduction about quantum computing intelligence technology. The Hellenic Robotics Center of Excellence at the National Technical University of Athens hosted a two-day session in December. Twenty-five students explored robotics and AI through hands-on design challenges such as TryEngineeringโs AI and machine learning methods. They also toured the universityโs research facilities. Hong Kong and Greek universities participate again The City University and St. Francis University in Hong Kong, and the University of Ioannina, Arta campus, Greece, participated in the program for a second year. Under the leadership of IEEE Senior Member Paulina Chan and volunteers from the IEEE Hong Kong Section, the City and St. Francis universities jointly held the program in July. They welcomed 55 students ages 12 to 18 from 41 schools. The students attended tutorials on foundational concepts and theories of AI. They worked in small teams on projects using AI-generated images, voice, and music manipulations. They were coached by students from St. Francis and Imperial College London. The participants presented their projects to judges, teachers, and parents. The students also visited a nearby semiconductor equipment manufacturer to learn about technology careers from engineers working there. The results of a post-program survey showed strong satisfaction with OnCampus, with nearly 75 percent of participants giving it a rating of 4 or higher out of 5. โI enjoyed getting to know about deep learning and its application,โ one student participant said. โThe content of the activity matched my interest, and I gained new knowledge.โ โOnCampus is led by a strong team with lots of experts in the field,โ another said. โItโs a rare chance for students to use software, learn about the theory behind how deep learning works, and get a glance at future possibilities.โ The University of Ioannina hosted the program in Arta in July with support from IEEE Senior Member Stamatis Dragoumanos and IEEE members Nikos Giannakeas and Eleftheria Kallinikou. Nearly 50 students, ages 12 to 16, attended the seven-day event, supported by 17 instructors and six volunteers from the universityโs IEEE student branch. The students learned about AI, augmented reality, microchip design, microcontrollers, and 3D printing. They also attended presentations by engineers from the industry. To give the students exposure to real-world engineering, they visited two hydroelectric power plants and a green data center. At the end of the program, students presented their projects and showcased the technical skills they had developed. Those involved in the TryEngineering OnCampus program are proud of the impactful experiences students have gained. The opportunities are possible because universities open their doors, share their expertise, and invest in the next generation of innovators. The University of Zagreb, the Arab Academy for Science, Technology, and Maritime Transport, the Majan University College, and The City University and St. Francis University will be participating again this year. To learn how you can bring the OnCampus program to your educational institution, send a request to tryengineering@ieee.org.
I used the Gemini app to generate lifelike videos featuring a digital clone of myself. Google sees this as the future of creation. Iโm still creeped out.
For years, the field of robotics has used the terms โdull, dirty, and dangerousโ (DDD) to describe the types of tasks or jobs where robots might be usefulโby doing work thatโs undesirable for people. A classic example of a DDD job is one of โrepetitive physical labor on a steaming hot factory floor involving heavy machinery that threatens life and limb.โ But determining which human activities fit into these categories is not as straightforward as it seems. What exactly is a โdullโ task, and who makes that assumption? Is โdirtyโ work just about needing to wash your hands afterwards, or is there also an aspect of social stigma? What data can we rely on to classify jobs as โdangerous?โ Our recent work (which was not dull at all) tackles these questions and proposes a framework to help roboticists understand the job context for our technology. First, we did an empirical analysis of robotics publications between 1980 and 2024 that mention DDD and found that only 2.7 percent define DDD and only 8.7 percent provide examples of tasks or jobs. The definitions vary, and many of the examples arenโt particularly specific (for example, โindustrial manufacturing,โ โhome careโ). Next, we reviewed the social science literature in anthropology, economics, political science, psychology, and sociology to develop better definitions for โdull,โ โdirty,โ and โdangerousโ work. Again, while it might seem intuitive which tasks to put into these buckets, it turns out that there are some underlying social, economic, and cultural factors that matter. Dangerous Work: Occupations or tasks that result in injury or risk of harm Itโs possible to measure the danger of a task or job by using reported information. There are administrative records and surveys that provide numbers on occupational injury rates and hazardous risk factors. While that seems straightforward, itโs important to understand how this data was collected, reported, and verified. First, occupational injuries tend to be underreported, with some studies estimating up to 70 percent of cases missing in administrative databases. Second, injuries and risk factors are rarely disaggregated by characteristics like gender, migration status, formal/informal employment, and work activities. For example, because most personal protective equipmentโsuch as masks, vests, and glovesโare sized for men, women in dangerous work environments face increased safety risks. These caveats are an opportunity for robotics to be helpful. If we went out and looked for it, we could probably find some less obviously dangerous work where robotics might be an important intervention, not to mention some groups that are disproportionately affected and would benefit from more workplace safety. Dirty Work: Occupations or tasks that are physically, socially, or morally tainted Colloquially, most people might think of dirty work as involving physical dirtiness, such as trash removal, cleaning, or dealing with hazardous substances. But social science literature makes clear that dirty work is also about stigma. Socially tainted jobs are often servile or involve interacting with stigmatized groups (for example, correctional officers), and morally tainted jobs include tasks that people commonly perceive as sinful, deceptive, or otherwise defying norms of civility (like a stripper or a collection agent). โDirty workโ is a social construct that can vary across time (like tattoo industry stigma in the United States) and culture (such as nursing in the U.S. versus in Bangladesh). One way to measure whether work is โdirtyโ is by using the closely related concept of occupational prestige, captured through quantitative surveys where people rank jobs. Another way to measure it is through qualitative data, like ethnographies and interviews. Similar to โdangerous,โ we see some hidden opportunities for robotics in โdirtyโ work. But one of our more interesting takeaways from the data is that a lower-ranked job can be something that the workers themselves enjoy or find immense pride and meaning in. If we care about what tasks are truly undesirable, understanding this worker perspective is important. Dull Work: Occupations or tasks that are repetitive and lacking in autonomy When it comes to defining dull work, what matters most is workersโ own experiences. Outsiders can make a lot of false assumptions about what tasks have value and meaning. Sometimes things that seem boring or routine create the right conditions for developing skills and competence, such as the concentration needed for woodworking, or for socializing and support, when tasks are done alongside others. Instead of assuming that repetitive work is negative, itโs important to examine qualitative data on how people experience the work and what purpose it serves for them. DDD: An actionable framework In our paper, we propose a framework to help the robotics community explore how automation impacts individual jobs. For each termโdull, dirty, and dangerousโthe framework gathers key pieces of information to reflect on what physical or social aspects of the task are, in fact, DDD. Worker perspective is an important part of all three considerations. The framework also emphasizes awareness of contextโmeaning the physical and social environment of an occupation and industry that can influence the DDD nature of a task. Our corresponding worksheet suggests existing data sources to draw on and encourages us to seek out multiple perspectives and consider potential sources of bias in the information. What makes tasks dull, dirty, or dangerous depends on the perspective of the humans doing those tasks.RAI Letโs take, for example, the waste and recycling industry. The world generates over 2 billion tonnes of waste annually, and this figure is expected to rise to nearly 4 billion tonnes by 2050. Intuitively, trash collection seems like a job that hits all the Ds. Going through our worksheet, we confirm that globally, workers in this industry face significant health hazards (dangerous), and waste collection is ranked as a low-status job (dirty), although interestingly, many workers take pride in providing this essential service. The job is also repetitive, but there are aspects that make it not dull. Specifically, workers cite the day-to-day interaction with their coworkers (which includes extensive insider vocabulary, work hacks, and mutual aid groups) and task variety as two of the most enjoyable aspects of the job. Task variety includes inspecting their vehicle and equipment, driving their truck, coordinating with crew members, lifting bins and bags, detecting incorrect sorting of waste, and unloading at the end destination. This finding matters because some types of robotic solutions will eliminate the parts of the job that workers most appreciate. For instance, the National Institute for Occupational Safety and Health (NIOSH) recommends the adoption of automated side loader trucks and collision avoidance systems. This innovation increases safety, which is great, but it also results in a sole worker operating a joystick in a cab, surrounded by sensor and camera surveillance. Instead, we should challenge ourselves to think of solutions that make jobs safer without making them terrible in a different way. To do this, we need to understand all aspects of what makes a job dull, dirty, or dangerous (or not). Our framework aims to facilitate this understanding. Finally, itโs important to note that DDD is only one of many possible approaches to classify what work might be better served by robots. There are lots of ways we could think about which types of tasks or jobs to automate (for example, economic impact or environmental sustainability). Given the popularity of DDD in robotics, we chose this common phrase as a starting point. We would love to see more work in this space, whether itโs data collection on DDD itself or the creation of other frameworks. At RAI, we believe that the fusion of robotics and social sciences opens a whole new world of information, perspectives, opportunities, and value. It fosters a culture of curiosity and mutual learning, and allows us to create actionable tools for anyone in robotics who cares about societal impact. Dull, Dirty, Dangerous: Understanding the Past, Present, and Future of a Key Motivation for Robotics, by Nozomi Nakajima, Pedro Reynolds-Cuรฉllar, Caitrin Lynch, and Kate Darling from the RAI Institute, was presented at the 21st ACM/IEEE International Conference on Human-Robot Interaction (HRI) in Edinburgh, Scotland.
Many of the worldโs most advanced electronic systemsโincluding Internet routers, wireless base stations, medical imaging scanners, and some artificial intelligence toolsโdepend on field-programmable gate arrays. Computer chips with internal hardware circuits, the FPGAs can be reconfigured after manufacturing. On 12 March, an IEEE Milestone plaque recognizing the first FPGA was dedicated at the Advanced Micro Devices campus in San Jose, Calif., the former Xilinx headquarters and the birthplace of the technology. The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly. The ceremony, which was organized by the IEEE Santa Clara Valley Section, brought together professionals from across the semiconductor industry and IEEE leadership. Speakers at the event included Stephen Trimberger, an IEEE and ACM Fellow whose technical contributions helped shape modern FPGA architecture. Trimberger reflected on how the invention enabled software-programmable hardware. Solving computingโs flexibility-performance tradeoff FPGAs emerged in the 1980s to address a core limitation in computing. A microprocessor executes software instructions sequentially, making it flexible but sometimes too slow for workloads requiring many operations at once. At the other extreme, application-specific integrated circuits are chips designed to do only one task. ASICs achieve high efficiency but require lengthy development cycles and nonrecurring engineering costs, which are large, upfront investments. Expenses include designing the chip and preparing it for manufacturingโa process that involves creating detailed layouts, building masks for the fabrication machines, and setting up production lines to handle the tiny circuits. โASICs can deliver the best performance, but the development cycle is long and the nonrecurring engineering cost can be very high,โ says Jason Cong, an IEEE Fellow and professor of computer science at the University of California, Los Angeles. โFPGAs provide a sweet spot between processors and custom silicon.โ Congโs foundational work in FPGA design automation and high-level synthesis transformed how reconfigurable systems are programmed. He developed synthesis tools that translate C/C++ into hardware designs, for example. At the heart of his work is an underlying principle first espoused by electrical engineer Ross Freeman: By configuring hardware using programmable memory embedded inside the chip, FPGAs combine hardware-level speed with the adaptability traditionally associated with software. Silicon Valley origins: the first FPGA The FPGA architecture originated in the mid-1980s at Xilinx, a Silicon Valley company founded in 1984. The invention is widely credited to Freeman, a Xilinx cofounder and the startupโs CTO. He envisioned a chip with circuitry that could be configured after fabrication rather than fixed permanently during creation. Articles about the history of the FPGA emphasize that he saw it as a deliberate break from conventional chip design. At the time, semiconductor engineers treated transistors as scarce resources. Custom chips were carefully optimized so that nearly every transistor served a specific purpose. Freeman proposed a different approach. He figured Mooreโs Law would soon change chip economics. The principle holds that transistor counts roughly double every two years, making computing cheaper and more powerful. Freeman posited that as transistors became abundant, flexibility would matter more than perfect efficiency. He envisioned a device composed of programmable logic blocks connected through configurable routingโa chip filled with what he described as โopen gates,โ ready to be defined by users after manufacturing. Instead of fixing hardware in silicon permanently, engineers could configure and reconfigure circuits as requirements evolved. Freeman sometimes compared the concept to a blank cassette tape: Manufacturers would supply the medium, while engineers determined its function. The analogy captured a profound shift in who controls the technology, shifting hardware design flexibility from chip fabrication facilities to the system designers themselves. In 1985 Xilinx introduced the first FPGA for commercial sale: the XC2064. The device contained 64 configurable logic blocksโsmall digital circuits capable of performing logical operationsโarranged in an 8-by-8 grid. Programmable routing channels allowed engineers to define how signals moved between blocks, effectively wiring a custom circuit with software. Fabricated using a 2-micrometer process (meaning that 2 ยตm was the minimum size of the features that could be patterned onto silicon using photolithography), the XC2064 implemented a few thousand logic gates. Modern FPGAs can contain hundreds of millions of gates, enabling vastly more complex designs. Yet the XC2064 established a design workflow still used today: Engineers describe the hardware behavior digitally and then โcompile the design,โ a process that automatically translates the plans into the instructions the FPGA needs to set its logic blocks and wiring, according to AMD. Engineers then load that configuration onto the chip. The breakthrough: hardware defined by memory Earlier programmable logic devices, such as erasable programmable read-only memory, or EPROM, allowed limited customization but relied on largely fixed wiring structures that did not scale well as circuits grew more complex, Cong says. FPGAs introduced programmable interconnectsโnetworks of electronic switches controlled by memory cells distributed across the chip. When powered on, the device loads a bitstream configuration file that determines how its internal circuits behave. โAs process technology improved and transistor counts increased, the cost of programmability became much less significant,โ Cong says. From โglue logicโ to essential infrastructure โInitially, FPGAs were used as what engineers called glue logic,โ Cong says. Glue logic refers to simple circuits that connect processors, memory, and peripheral devices so the system works reliably, according to PC Magazine. In other words, it โgluesโ different components together, especially when interfaces change frequently. Early adopters recognized the advantage of hardware that could adapt as standards evolved. In โThe History, Status, and Future of FPGAs,โ published in Communications of the ACM, engineers at Xilinx and organizations such as Bell Labs, Fairchild Semiconductor, IBM, and Sun Microsystems said the earliest uses of FPGAs were for prototyping ASICs. They also used it for validating complex systems by running their software before fabrication, allowing the companies to deploy specialized products manufactured in modest volumes. Those uses revealed a broader shift: Hardware no longer needed to remain fixed once deployed. Attendees at the Milestone plaque dedication ceremony included (seated L to R) 2025 IEEE President Kathleen Kramer, 2024 IEEE President Tom Coughlin, and Santa Clara Valley Section Milestones Chair Brian Berg.Douglas Peck/AMD Semiconductor economics changed the equation The rise of FPGAs closely followed changes in semiconductor economics, Cong says. Developing a custom chip requires a large upfront investment before production begins. As fabrication costs increased, products had to ship in large quantities to make ASIC development economically viable, according to a post published by AnySilicon. FPGAs allowed designers to move forward without that larger monetary commitment. ASIC development typically requires 18 to 24 months from conception to silicon, while FPGA implementations often can be completed within three to six months using modern design tools, Cong says. The shorter cycle and the ability to reconfigure the hardware enabled startups, universities, and equipment manufacturers to experiment with advanced architectures that were previously accessible mainly to large chip companies. Lookup tables and the rise of reconfigurable computing A popular technique for implementing mathematical functions in hardware is the lookup table (LUT). A LUT is a small memory element that stores the results of logical operations, according to โLUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs,โ a paper selected for presentation next month at the 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). Instead of repeatedly recalculating outcomes, the chip retrieves answers directly from memory. Cong compares the approach to consulting multiplication tables rather than recomputing the arithmetic each time. Research led by Cong and others helped develop efficient methods for mapping digital circuits onto LUT-based architectures, shaping routing and layout strategies used in modern devices. As transistor budgets expanded, FPGA vendors integrated memory blocks, digital signal-processing units, high-speed communication interfaces, cryptographic engines, and embedded processors, transforming the devices into versatile computing platforms. Why the gate arrays are distinct from CPUs, GPUs, and ASICs FPGAs coexist with other processors because each one optimizes different priorities. Central processing units excel at general computing. Graphics processing units, designed to perform many calculations simultaneously, dominate large parallel workloads such as AI training. ASICs provide maximum efficiency when designs remain stable and production volumes are high. โASICs can deliver the best performance, but the development cycle is long, and the nonrecurring engineering cost can be very high. FPGAs provide a sweet spot between processors and custom silicon.โ โJason Cong, IEEE Fellow and professor of computer science at UCLA. โFPGAs are not replacements for CPUs or GPUs,โ Cong says. โThey complement those processors in heterogeneous computing systems.โ Modern computing platforms increasingly combine multiple types of processors to balance flexibility, performance, and energy efficiency. A Milestone for an idea, not just a device This IEEE Milestone recognizes more than a successful semiconductor product. It also acknowledges a shift in how engineers innovate. Reconfigurable hardware allows designers to test ideas quickly, refine architectures, and deploy systems while standards and markets evolve. โWithout FPGAs,โ Cong says, โthe pace of hardware innovation would likely be much slower.โ Four decades after the first FPGA appeared, the technologyโs enduring legacy reflects Freemanโs insight: Hardware did not need to remain fixed. By accepting a small amount of unused silicon in exchange for adaptability, engineers transformed chips from static products into platforms for continuous experimentationโturning silicon itself into a medium engineers could rewrite. Among those who attended the Milestone ceremony were 2025 IEEE President Kathleen Kramer; 2024 IEEE President Tom Coughlin; Avery Lu, chair of the IEEE Santa Clara Valley Section; and Brian Berg, history and milestones chair of IEEE Region 6. They joined AMDโs chief executive, Lisa Su, and Salil Raje, senior vice president and general manager of adaptive and embedded computing at AMD. The IEEE Milestone plaque honoring the field-programmable gate array reads: โThe FPGA is an integrated circuit with user-programmable Boolean logic functions and interconnects. FPGA inventor Ross Freeman cofounded Xilinx to productize his 1984 invention, and in 1985 the XC2064 was introduced with 64 programmable 4-input logic functions. Xilinxโs FPGAs helped accelerate a dramatic industry shift wherein โfablessโ companies could use software tools to design hardware while engaging โfoundryโ companies to handle the capital-intensive task of manufacturing the software-defined hardware.โ Administered by the IEEE History Center and supported by donors, the IEEE Milestone program recognizes outstanding technical developments worldwide that are at least 25 years old. Check out Spectrumโs History of Technology channel to read more stories about key engineering achievements.