Reducing Power Consumption of Embedded Dynamic Memories with ECCs

Gain-cell embedded dynamic random-access memory (GCRAM) offers dense and energy-efficient on-chip storage, but retention-time variations force frequent refresh operations to cover worst-case bits.

Error-correction codes (ECCs) can alleviate this limitation by masking bit errors from weak cells and thereby reduce refresh cost.

However, the trade-off between the additional access and logic energy introduced by ECCs and the power savings from longer refresh intervals is nontrivial, especially considering the wide range of available ECC options.

To optimize overall power consumption, we propose an ECC selection method that combines a refresh-interval model with power analysis to identify the minimum-power ECC configurations under a given yield constraint.

Across different memory bandwidths, activity factors, and read/write ratios, the evaluation results show that the best ECC option shifts from stronger codes in refresh-dominated operating regions to lower-overhead codes in access-dominated regions and achieves 46.8% to 94.8% reduction in total power relative to the no-ECC reference.