Fortune
์ค๋ ์ฑํฅ
IT/๊ธฐ์
The AI tradeโs worst day in a year became a buying opportunity by Monday
Fridayโs Nasdaq rout looked like the start of a real repricing. By Monday, chipmakers were rebounding.
๐บ๐ธ ๋ฏธ๊ตญ ยท "CHIPMAKERS" ยท ์ด 6๊ฑด
ํํฐ ๋ณด๊ธฐํ์ฌ ์ง์
48.9
0 = ๋ถ์ ์ฐ์ธ
50 = ์ค๋ฆฝ
100 = ๊ธ์ ์ฐ์ธ
์ต๊ทผ 7์ผ ๊ธฐ์ค 10,349๊ฑด์ ๋ถ์ํ ๊ฒฐ๊ณผ, ๋ด์ค ์ฌ๋ฆฌ์ง์๋ 48.9(๊ท ํ)์ ๋๋ค. ๊ธ์ 1,026๊ฑด(9.9%)ยท์ค๋ฆฝ 7,470๊ฑด(72.2%)ยท๋ถ์ 1,853๊ฑด(17.9%)์ด๋ฉฐ, ์ค๋ฆฝ ๋น์ค์ด ๋๋ ทํ๊ฒ ๋์ต๋๋ค. ์ฑํฅ ์ง์๋ ์ข ํฉ 20.9(๋ณด์ ๊ฒฝํฅ)์ ๋๋ค.
Fridayโs Nasdaq rout looked like the start of a real repricing. By Monday, chipmakers were rebounding.
The S&P 500 and Nasdaq were up as chipmakers rebounded after Friday's brutal selloff.
U.S. chipmakers plunged in premarket trading after Broadcom earnings disappointed investors.
I have been an application-specific IC (ASIC) designer for almost three decades. Over that time, Iโve moved through the full academic trajectory, from graduate student to full professor; later, I transitioned to industry after an unsuccessful stint at entrepreneurship. When I made the switch to the private sector in 2019, I began focusing on a critically important aspect of the electronic industry: silicon intellectual property. As much as 80 percent of the physical area in todayโs most advanced chips is occupied by blocks that arenโt made for specific products or even designed by the consumer-facing companies that built them. Instead, chipmakers draw heavily on established silicon IP from companies like Arm, Cadence, Rambus, Synopsys, and the company I work for, Silicon Creations. Throughout my career, Iโve designed chips for very different purposes, including enabling the research program in my academic lab and expanding the IP portfolio of my company. When I joined Silicon Creations, I had no idea how differently the industry approaches IC design and encountered a steep learning curve. Initially, it seemed that much of my two decades of academic research and training did not directly translate to the role. I had to learn new skills and adopt a new mindset. Today, demand for ASICs is rapidly growing, driven by the need for specialized chips in the automotive sector, AI applications, and more. By one market estimate, the ASIC market is expected to grow from US $23.4 billion to $38.8 billion by 2033, and the semiconductor industry as a whole is projected to hit $1 trillion by 2030. The industry needs more chip designersโbut if youโre coming from an academic background as I did, there are a few things youโll need to know. Different goals lead to different strategies The differences between industry and academe begin with a divergence in purpose. In academia, my primary objective was to generate new knowledge: to propose a novel circuit technique, validate an unconventional architecture, or explore the limits of performance in a given domain. A successful chip is one that demonstrates a concept. In industry, it is not nearly enough to prove that something can work. The goal is to ensure that it works reliably, repeatedly, and at scale. Success is measured not by novelty but by whether the silicon meets specifications, yields as expected in production, and supports a competitive product delivered on schedule. This leads to a stark contrast in risk tolerance. Academic designs often deliberately push into unproven territory, where even partial success can yield valuable insight. In industry, however, we systematically minimize risk. The cost of failure makes first-time silicon success a central requirementโespecially at advanced technology nodes, where the lithography masks used to transfer circuit designs onto silicon wafers alone can cost tens of millions of dollars. As a result, industry design flows are built around eliminating uncertainty through conservative margins, extensive validation, and careful reuse of proven solutions. โAcademia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale.โ This paradigm has existed since the 1970s, when application-specific chip design was established. However, the gulf between academia and industry has expanded since the mid-2010s, when FinFET technology, a 3D architecture using vertical โfinsโ of silicon, was widely adopted in industry. System designs are also becoming increasingly modular with the advent of chiplets. This fundamentally altered the economics and complexity of ASIC development, with design costs rising by almost an order of magnitude. Initiatives like Taiwan Semiconductor Manufacturing Co.โs University FinFET Program and new government-funded chip-design hubs now let some well-resourced universities design for more advanced architectures, but the technology is still out of reach for many academics. What the industry-academia split means in practice Consider a startup developing an ASIC. Its engineering team may have deep expertise in a particular algorithm, sensor interface, or system architecture, the features that define its competitive advantage. But it is unlikely to possess world-class expertise in every supporting function. Developing each of these blocks internally would require significant time, capital, and specialized talent. Doing so could delay market entry beyond the startupโs viability. Even large semiconductor companies face similar constraints. Advanced-node development demands intense focus. Allocating a team to redesign a standard interface block that has already been implemented elsewhere may be difficult to justify when differentiation lies at the system level, such as an inference chipโs ability to speed up neural network computations. The time it takes to move a new chip from conception to market and risk mitigation, not self-sufficiency, govern most decisions about in-house development versus outsourcing. The economics of advanced IC manufacturing reinforce this reality. When the development cost of a leading-edge chip reaches hundreds of millions of dollars, minimizing risk becomes a central design imperative. In this context, silicon IP emerged as a practical solution. Similar to how software developers rely on preexisting libraries rather than writing every function from scratch, ASIC designers license predesigned, preverified silicon blocksโsuch as processor cores, memory interfaces, and security enginesโfrom highly specialized IP vendors. These blocks can then be integrated into larger, increasingly complex systems. Design scope, verification, and time horizons With the use of silicon IP, industry is able to widen the scope of its designs. Academic efforts tend to focus on block-level innovation: a new analog-to-digital converter architecture or an ultralow-noise amplifier, for instance. These designs typically abstract away many of the complexities of bringing a chip to market, such as packaging constraints, long-term reliability, and manufacturing yield. In industry, the focus shifts to system-level integration. Modern systems on chips, or SoCs, incorporate dozens or even hundreds of functional blocks. Managing signal integrity, timing, firmware interaction, and system-level validation becomes as critical as the design of any individual block. Verification philosophy also diverges sharply. In academia, the goal of verification is to demonstrate that the concept works under nominal conditions, which may not always reflect how it would perform in real applications. Even if only a fraction of fabricated chips from a multiproject wafer operates correctly, the design may still be considered a success if it validates the underlying idea. At my academic lab for instance, we used to receive 40 chips from a TSMC prototyping service and started testing them in batches of five. If the first five or 10 chips proved functional, we had already collected more than enough data for a publication. If some of them failed, we werenโt required to mention this when publishing the results. In industry, verification is exhaustive, critical, and often dominates the development schedule. Failures are measured in parts per million, and even rare anomalies are carefully analyzed and documented to identify root causes and prevent recurrence. When I started at Silicon Creations, I was surprised by the level of detail and scrutiny designs face. Differences in time horizons and economic constraints reinforce each of these contrasts. Academic projects operate on flexible timelines aligned with research and funding cycles. If I missed a deadline, I just had to wait for the next cycle. Industry projects are driven by fixed product schedules and market windows, frequently targeting costly leading-edge nodes to achieve competitive performance, power, and area efficiency. Missing a deadline can negate the value of an entire design and may have major financial consequences along the entire supply chain. In essence, academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale. Both are indispensable, but they operate under fundamentally different definitions of success. As ASIC complexity continues to grow, understanding both perspectives will be essential for the next generation of engineers navigating the evolving semiconductor landscape. This article appears in the June 2026 print issue.
A global memory shortage driven by AI is spiking demand for chipmakers like Micron.
This sponsored article is brought to you by Applied Materials. At pivotal moments in history, progress has required more than individual brilliance. The most consequential breakthroughs โ such as those achieved under the Human Genome Project โ required a new operating paradigm: Concentrate the worldโs best talent around a single mission, establish a common platform, share critical infrastructure, and collapse feedback loops. When stakes are high and timelines are compressed, sequential and siloed innovation simply cannot keep pace. Todayโs AI era is creating an engineering race with similar demands. Every company is pushing to deliver higher-performance AI systems, faster. But performance is no longer defined by compute alone. AI workloads are increasingly dominated by the movement of data: In many cases, moving bits consumes as much โ or more โ energy than compute itself. As a result, reducing energy per bit can extend systemโlevel performance alongside gains in peak compute. The path to energyโefficient AI therefore runs through systemโlevel engineering, spanning three tightly interconnected domains: Logic, where performance per watt depends on efficient transistor switching, lowโloss power, and signal delivery through dense wiring stacks. Memory, where surging bandwidth and capacity demands expose the memory wall, with processor capability advancing faster than memory access. Advanced packaging, where 3D integration, chiplet architectures, and highโdensity interconnects bring compute and memory closer together โ enabling system designs monolithic scaling can no longer sustain. These domains can no longer be optimized independently. Gains in logic efficiency stall without sufficient memory bandwidth. Advances in memory bandwidth fall short if packaging cannot deliver proximity within thermal and mechanical constraints. Packaging, in turn, is constrained by the precision of both frontโend device fabrication and backโend integration processes. In the angstrom era, the hardest problems arise at the boundaries โ between compute and memory in the package, frontโend and backโend integration, and the tightly coupled process steps needed for precise 3D fabrication. And it is precisely this boundaryโdriven complexity where the traditional innovation model breaks down. The Traditional R&D Workflow Is Too Slow for AngstromโEra AI For decades, the semiconductor industryโs R&D model has resembled a relay race. Capabilities are developed in one part of the ecosystem, handed off downstream through integration and manufacturing, evaluated by chip and system designers, and only then fed back for the next iteration. That model worked when progress was dominated by relatively modular steps that could be scaled independently and simply dropped into the manufacturing flow. But the AI timeline has upended these rules. At angstromโscale dimensions, the physics enforces inescapable coupling across the entire stack: materials choices shape integration schemes; integration defines design rules; design rules dictate power delivery; wiring sets thermal budgets; and thermals ultimately constrain packaging scaling. System architects simply cannot wait 10โ15 years for each major semiconductor technology inflection to mature. Representing a roughly $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history. A longโterm perspective is essential to align materials innovation with emerging device architectures โ and to develop the tools and processes required to integrate both with manufacturable precision. At Applied Materials, together with our customers, we are charting a course across the next 3โ4 generations, extending as far as 10 years down the roadmap. The angstrom era demands that we break down silos and bring together the industryโs best minds โ from leading companies to leading academic institutions. If the problem is coupled, the solution must be coupled. If the timeline is compressed, the learning loop must be compressed. Itโs not enough to just innovate โ we must innovate how we innovate. EPIC: A Center and Platform for HighโVelocity CoโInnovation This is the challenge that Applied Materials EPIC Center is designed to solve. Representing a roughly US $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history. When it opens in 2026, it will deliver stateโofโtheโart cleanroom capabilities built from the ground up to shorten the path from earlyโstage research to fullโscale manufacturing. But the facilities are only one component of the model. EPIC is also a platform, an operating system for high-velocity coโinnovation that revolutionizes how ideas move from the lab to the fab. EPIC is a platform, an operating system for high-velocity coโinnovation that revolutionizes how ideas move from the lab to the fab.Applied Materials The EPIC model compresses the traditional workflow. Customer engineers work sideโbyโside with Applied technologists from day one โ moving beyond isolated process optimization and downstream handoffs. Within a shared, secure environment, EPIC tightly integrates atomistic modeling, test vehicles, process development, validation, and metrology feedback. Constraints that once surfaced late in development are identified and addressed early. The result is a potentially 2x faster path that benefits the entire ecosystem under one roof: Chipmakers gain earlier access to Appliedโs R&D portfolio, faster learning cycles, and accelerated transfer of nextโgeneration technologies into highโvolume manufacturing. Ecosystem partners gain earlier access to advanced manufacturing technology and collaboration opportunities that expand what is possible through materials innovation. Academic institutions gain opportunities to strengthen the labโtoโfab pipeline and help develop future semiconductor talent. Building on decades of coโdevelopment, we are reinventing the innovation pipeline with our partners across logic, memory, and advanced packaging to deliver the next leap in energyโefficient AI. Accelerating Advanced Logic Logic remains the engine of AI compute. In the angstrom era, however, systemโlevel gains are increasingly constrained by power and energy. Extending AI performance now depends on architectures that deliver more performance per watt โ accelerating the move to 3D devices such as gateโallโaround (GAA) transistors, which boost density within a compact footprint while preserving power efficiency. Architectures that deliver more performance per watt are accelerating the move to 3D devices such as gateโallโaround (GAA) transistors, and further out, complementary FETs (CFETs), which push density scaling even more.Applied Materials These architectural shifts are unfolding at unprecedented scale, with the logic roadmap already extending beyond firstโgeneration GAA toward more advanced designs. One key example is GAA with backside power delivery, which relocates thick power lines to the backside of the wafer, reducing resistive losses and freeing frontโside routing for tighter logic cell integration. Another example brings adjacent GAA PMOS and NMOS transistors closer together while inserting a dielectric isolation wall between them to minimize electrical interference. Further out, complementary FETs (CFETs) push density scaling even more by stacking PMOS and NMOS devices directly atop one another. While these architectures deliver compelling gains in performance per watt and logic density without relying solely on tighter lithography, they significantly raise integration complexity. Manufacturing a single GAA device today can involve more than 2,000 tightly interdependent process steps. At the same time, wiring stacks continue to grow taller and denser to connect these advanced logic devices. Modern leadingโedge GPUs now in development pack more than 300 billion transistors into an area little larger than a postage stamp, interconnected by over 2,000 miles of wiring. Modern leadingโedge GPUs now in development pack more than 300 billion transistors into an area little larger than a postage stamp, interconnected by over 2,000 miles of wiring.Applied Materials At this level of complexity, the process steps used to create these precise 3D devices and wiring stacks cannot be optimized independently. Design and process must evolve in lockstep, and materials innovation and fabrication methods must advance alongside device architecture. EPICโs coโinnovation model is designed to accelerate exactly this convergence โ enabling logic compute to continue advancing the frontiers of AI at the pace the roadmap demands. Powering the Memory Roadmap At the same time, the AI computing era is fundamentally reshaping how data is generated, moved, and processed โ making memory technologies, especially DRAM, central to delivering the energyโefficient performance AI systems require. As models grow larger and more dataโhungry, the DRAM roadmap is shifting toward architectures that deliver higher density, greater bandwidth, and faster access per watt. At the DRAM cell level, AI performance requirements are driving a transition from 6Fยฒ buriedโchannel array transistors (BCAT) to more compact 4Fยฒ, and beyond that, architectures that move past what 2D scaling alone can deliver. Applied Materials At the DRAM cell level, this shift is driving a transition from 6Fยฒ buriedโchannel array transistors (BCAT) to more compact 4Fยฒ architectures, which orient the transistor vertically to boost density and reduce chip area. Looking beyond 4Fยฒ, sustaining gains in performance per watt will require moving past what 2D scaling alone can deliver. The industry is therefore turning to 3D DRAM, stacking memory cells vertically to add capacity within a constrained footprint. As these structures grow taller and aspect ratios intensify, high-mobility materials engineering in three dimensions becomes increasingly critical to performance and reliability. Beyond the memory cell array, another powerful lever for DRAM scaling is shrinking the peripheral circuitry, which includes logic transistors and interconnect wiring. One emerging approach places select periphery functions beneath the DRAM array by bonding two wafers โ one optimized for the DRAM cells and the other for CMOS logic โ using multiple wiring layers. Beyond the memory cell array, another powerful lever for DRAM scaling is shrinking the peripheral circuitry, which includes logic transistors and interconnect wiring.Applied Materials In parallel, DRAM performance is being extended by leveraging logicโproven enhancers in the memory periphery. These include mobility boosters such as embedded silicon germanium and stress films, along with wiring upgrades like improved lowโk dielectrics and advanced copper interconnects. Memory manufacturers are also transitioning periphery transistors from planar devices to FinFET architectures, following the logic roadmap to further improve I/O speed. These valuable inflections are central to EPICโs mission โ where they can be co-developed and rapidly validated for nextโgeneration memory systems. Driving System Scaling With Advanced Packaging As data movement becomes the dominant energy cost in AI systems, advanced packaging has emerged as a critical lever for improving systemโlevel efficiencyโshortening interconnect distances, increasing bandwidth density, and reducing the power required to move data between logic and memory. The rise of 3D packages such as highโbandwidth memory (HBM) underscores why advanced packaging is becoming central to the AI era.Applied Materials Highโbandwidth memory (HBM) marks a major inflection along this path. By stacking DRAM dies โ scaling to 16 layers and beyond โ and placing memory much closer to the processor, HBM enables rapid access to everโlarger working datasets. This delivers stepโfunction gains in both bandwidth and energy efficiency. More broadly, the rise of 3D packages such as HBM underscores why advanced packaging is becoming central to the AI era. Packaging now addresses systemโlevel constraints that logic and memory device scaling alone can no longer overcome. It also enables a move away from monolithic systemsโonโchip toward chipletโbased architectures, as AI workloads increasingly demand flexible designs that combine logic, memory, and specialized accelerators optimized for specific tasks. A vital technology powering this roadmap is hybrid bonding. With interconnect pitches approaching those of onโchip wiring, conventional bumps and microbumps run into fundamental limits in density, power, and signal integrity. Hybrid bonding removes these barriers by allowing dramatically higher interconnect and I/O density, supporting a broad range of chiplet architectures โ from memory stacking to tighter computeโmemory integration. EPIC tackles highโvalue advancedโpackaging challenges through early, parallel coโinnovation across materials, integration, and manufacturing.Applied Materials As bonded structures like HBM stacks grow larger and more complex, warpage control, die placement, stack alignment, and thermal management become firstโorder challenges. EPIC tackles these and other highโvalue advancedโpackaging challenges through early, parallel coโinnovation across materials, integration, and manufacturing. Bringing It All Together Across logic, memory, and advanced packaging, our industry faces an ambitious roadmap that promises significant gains in energy efficiency for AI systems. But realizing that potential demands breakthrough materials innovation at a time when feature sizes are shrinking, interfaces are multiplying, and process interdependencies are escalating. These challenges cannot be solved on 10โ15โyear timelines under the traditional relayโrace model. We must break down silos, align earlier across the ecosystem, and parallelize learning to keep pace with AIโs demands. In the AI era, progress will be defined by the speed at which lightbulb moments turn into manufacturing and commercialization reality. The only viable path forward is a new innovation model โ and EPIC is how we are driving it.